Devices and methods for expanding the memory capacity in digital computers are, of course, well-known in the computer art. Known techniques for accomplishing memory expansion range from the "over-capacity" approach at one extreme to "brute force" approaches at the other. In the typical over-capacity approach both software and hardware expansion provisions are made in advance, and the expansion devices are merely inserted at some later time into the host system if and when needed. The brute force, or ad hoc approaches, include schemes where memory expansion devices are added by conventional hard wiring in the expansion memory circuits, and inserting adjunct circuitry including code and level converters, control logic conversions, and the inevitable additional power supplies.
To a considerable degree, the approach used depends on the configuration of the host system which is to be expanded, and on the degree of retrofit complexity that can be tolerated. Prior art approaches have tended to be based on static memory devices, and on the assumption that retrofit modifications are tolerable. The present invention is a significant departure from these approaches and can work with both static and dynamic memory devices, but is especially advantageous when using dynamic memory expansion. Dynamic memory expansion is denser, more cost effective, and less power consumptive than static memory. However, by its nature, dynamic memory requires considerably more electronic overhead, such as, for refresh operations and address multiplexing than static memory, and the implementation of this electronic overhead can be very complex and demanding. Employing the new method of dynamic memory expansion in accordance with the present invention eliminates the need for the design and implementation of such electronic overhead, thus allowing a simple and economically very attractive method of expansion with a minimum of modifications to the existing host computer system.
Illustrative prior art patents which teach a variety of computer memory expansion approaches are found in U.S. Pat. No. 3,972,025 to Taddei, U.S. Pat. No. 3,967,251 to Levine, and U.S. Pat. No. 3,292,151 to Barnes et al.